module handmst (/*AUTOARG*/ // Outputs act, finish, req, // Inputs clk, xrst, start, ack ); // public // private parameter P_DELAY = 1; parameter P_INIT = 2'd0; parameter P_REQ = 2'd1; parameter P_WAIT = 2'd2; input clk ; // I : input xrst ; // I : input start ; // I : output act ; // O : output finish ; // O : output req ; // O : input ack ; // I : reg [1:0] w_state ; reg [1:0] r_state ; reg r_req ; reg r_ack0 ; reg r_ack1 ; wire w_act ; reg r_finish ; assign act = w_act; assign finish = r_finish; assign req = r_req; // w_state[1:0] always @(/*AS*/r_ack1 or r_state or start) begin case (r_state) P_INIT: if (start == 1'b1) begin w_state = P_REQ; end else begin w_state = r_state; end P_REQ: if (r_ack1 == 1'b1) begin w_state = P_WAIT; end else begin w_state = r_state; end P_WAIT: if (r_ack1 == 1'b0) begin w_state = P_INIT; end else begin w_state = r_state; end default: w_state = P_INIT; endcase end // r_state[1:0] always @(posedge clk or negedge xrst) begin if (!xrst) begin r_state <= #P_DELAY P_INIT; end else begin r_state <= #P_DELAY w_state; end end // r_req always @(posedge clk or negedge xrst) begin if (!xrst) begin r_req <= #P_DELAY 1'b0; end else if (r_state == P_INIT && w_state == P_REQ) begin r_req <= #P_DELAY 1'b1; end else if (r_state == P_REQ && w_state == P_WAIT) begin r_req <= #P_DELAY 1'b0; end end // r_ack0 // r_ack1 always @(posedge clk or negedge xrst) begin if (!xrst) begin r_ack0 <= #P_DELAY 1'b0; r_ack1 <= #P_DELAY 1'b0; end else begin r_ack0 <= #P_DELAY ack; r_ack1 <= #P_DELAY r_ack0; end end // w_act assign w_act = (r_state != P_INIT); // r_finish always @(posedge clk or negedge xrst) begin if (!xrst) begin r_finish <= #P_DELAY 1'b0; end else if (r_state == P_WAIT && w_state == P_INIT) begin r_finish <= #P_DELAY 1'b1; end else begin r_finish <= #P_DELAY 1'b0; end end endmodule